In digital telecommunications systems that transmit digital data, signal errors can be generated in digital data in the process of transmission, so encoding is carried out through the use of error-correcting codes for the digital data to be sent.
If the number of erroneous bits in one code word is kept below a specified value when creating these error-correcting codes, then it is possible to correct all of the errors at the time of error-correcting decoding on the receiving side. The number of bits that can be corrected per code word is known as the error correcting capacity of the error-correcting code.
Although the average code error rate itself is low in telecommunications environments such as mobile telecommunications, burst errors readily occur. Consequently, even if data is transmitted with error correction encoding, burst errors often occur with the number of consecutive bits exceeding the error correcting capacity.
For this reason, the use of error-correcting codes in mobile telecommunications environments is less effective than in telecommunications environments where random code errors are generated. Accordingly, interleaving is used to solve this problem.
Interleaving is a technique for scrambling the order of a bit sequence that is to be sent, so as to transmit the bits in a sequence that differs from the original order.
The method of interleaving is described here with one example, using as a unit a bit sequence of m×n bits consisting of a collection of m code words formed from n bits. It should be noted that for the sake of convenience, a bit sequence for one instance of interleaving shall be referred to as a frame.
Generally speaking, interleaving utilizes memory. In this example, interleaving is carried out through the use of a continuous storage area of m×n in memory.
FIG. 20 shows this interleaving storage area expressed as a two-dimensional memory space. The storage areas in this memory space are specified by address data with a specified number of bits formed from a lower address that can take n combination of values and an upper address that can take m combination of values. In FIG. 20, storage areas with identical upper addresses are arranged from left to right in lower address sequence, and storage areas with identical lower addresses are arranged from top to bottom in upper address sequence. It should be noted that hereinafter, for the sake of convenience, a series of storage areas with identical upper addresses shall be called rows, and a series of storage areas with identical lower addresses shall be called columns.
When implementing interleaving, first of all, the bit sequences in question are each to be written sequentially in their respective m×n storage area, one bit at a time. When carrying out this writing, the writing addresses are generated by an address-generating circuit such as shown in FIG. 21, for example. This address-generating circuit is formed from an n-scale counter 11 and an m-scale counter 12. Here, then-scale counter 11 conducts a count of the bit clock synchronous with the input timing of the bits that are to be interleaved. The m-scale counter 12 increases the count value by “1” for each nth change in the count value of the n-scale counter 11. In addition, the writing address consisting of the count value of the n-scale counter 11 as the lower address and the count value of the m-scale counter 12 as the upper address is provided to the memory shown in FIG. 20, and these are written to memory.
Consequently, as shown in FIG. 22, the code word of the initial n bit in the bit sequence is written in the first row in the memory space, the next code word is written in the second row, and so forth, so that ultimately, the mth code word is written in the mth row.
Next, the various bits that are thusly written into memory are read in an order that differs from when they were written.
In this reading operation, a reading address is generated by the address-generating circuit shown in FIG. 23. In the configuration shown in FIG. 23, a count of bit blocks is conducted by an m-scale counter 22, and this m-scale counter 22 increases the count value by “1” for each mth change in the count value of an n-scale counter 21. In addition, the reading address consisting of the lower address with the count value of the n-scale counter 21 and the upper address with the count value of the m-scale counter 22 is supplied to the memory for interleaving synchronously with the bit block, and readout of memory is implemented.
Consequently, as shown in FIG. 24, the m bits recorded in each storage area of the first column of the memory space are read in the upper address sequence, then the m bits recorded in each storage area of the second column are read in the upper address sequence, and so forth, so that ultimately, the m bits recorded in each storage area of the n column are read in the upper address sequence.
Accordingly, the bits forming the code words are distributed over the entire area within the frame by virtue of the fact that the code words forming the frame are written into memory, and by virtue of the fact that the bits forming the code words are read in a sequence that differs from when they were written. In further detail, as a result of interleaving, the n bits forming the code words are scattered and arranged within the frame in such a state that they are separated by inserting them between the m−1 bits belonging to other code words.
After implementing such interleaving, the frame is delivered to the transmission pathway.
When the receiving side receives the frame via the transmission pathway, a scrambling operation is executed which is the reverse of interleaving, thereby recovering the frame with the bit sequence in the original order. This scrambling operation occurring on the receiving side is known as de-interleaving.
When frames are transmitted using a transmission method that deploys such interleaving and de-interleaving, it becomes easy to correct signal errors on the receiving side, even if the burst errors occur in the frames during the transmission process.
A more detailed description is given below.
First, suppose that a burst error with a bit length of m×k occurs in an interleaved frame during the transmission process.
Here, a burst error occurring with a bit length of m×k contains k bits each per code word, said bits forming m code words. Accordingly, bits that are affected by burst errors in the m code words recovered by de-interleaving are only k bits per code word. That is to say, said code error becomes a random code error for the frame after de-interleaving.
Therefore, in cases where error correction encoding of code words is performed through the use of error-correcting codes capable of correcting errors numbering more than k bits, it becomes possible to correct all signal errors on the receiving side even if burst errors occur with a bit length of m×k.
It should be noted here that, for the sake of convenience, the effect which is brought about by interleaving is referred to below as randomization of burst errors, or simply as randomization.
In cases where the number m of code words making up a frame is large, the number of erroneous bits per code word can be reduced, even if burst errors are generated that have high bit lengths. In this sense, it may well be the case that, the greater the number m of code words making up the frame, the greater the randomization effect imparted by interleaving.
However, since it is necessary to store at least one frame's worth of bits in order to deploy interleaving on the transmission side and deinterleaving on the receiving side, respectively, a delay unavoidably occurs. Accordingly, the frame length for interleaving must be selected in such a way as to reduce the delay. To this end, it is considered desirable to set a frame length as an interleaving processing unit that is equal to the frame length set by the CODEC and the like.
Incidentally, in the case of digital transmission of data such as voice and images, there are instances where the bit sequence forming one frame that serves as the unit of transmission is composed of a header that has undergone error correction encoding and a portion that has not undergone error correction encoding. When said interleaving is executed with respect to the entire bit sequence forming such a single frame, the following problems occur since randomization of burst errors is also carried out on portions that have not undergone error correction encoding.
(1) Problem 1
In the case of a CODEC that handles data such as voice and the like, when errors are predicted to occur in portions that have not undergone error correction encoding, an operation is executed that is known as concealment, whereby said portion is substituted into a non-sound sector. It is more desirable that the signal errors be concentrated, so that such an operation is executed appropriately. Thus, randomization due to interleaving is not desirable in relation to portions that have not undergone error correction encoding.
(2) Problem 2
In order to optimize the effect of randomization due to interleaving, it is desirable to deploy interleaving while using as a standard the bit length n of the code words that have undergone error correction encoding, and widely scattering the n bits forming each code word within one frame. However, in actual practice, different types of error correction encoding are executed, depending on the type of data to be transmitted, and there are many cases where one frame is formed from a plurality of types of code words (or error correction codes). In such cases, a sufficient randomization effect can be realized with regard to a specified error correction code when interleaving is deployed across an entire frame using as a standard the code length of said specified error correction code within the frame, but there arises the problem that a sufficient randomization effect is not realized with regard to other error correction codes with different code lengths.
(3) Problem 3
The determination of whether randomization is advantageous or not does not depend only on whether or not there is data that has undergone error correction encoding. That is to say, in frames formed from bit sequences that have undergone error correction encoding and bit sequences that have not undergone error connection encoding, there are cases where those bit sequences that have not undergone error correction encoding are, by their nature, either formed in response to data which should be randomized, or formed in response to data which should not be randomized. For each datum forming a frame, it would be advantageous to determine whether or not randomization is appropriate by seeking an approach that suits the nature of the data in question, but until now, no technological means have been provided for this purpose.